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A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth.
Pratap Tumkur Renukaswamy
Nereo Markulic
Piet Wambacq
Jan Craninckx
Published in:
IEEE J. Solid State Circuits (2020)
Keyphrases
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clock frequency
power consumption
dielectric constant
high speed
low power
frequency band
simulation software
low frequency
high end
parallel architecture
error rate
high frequency
fourier transform
parallel computing
root mean square
space variant
real time