A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
Lucas Moura SantanaEwout MartensJorge LagosBenjamin P. HershbergPiet WambacqJan CraninckxPublished in: IEEE J. Solid State Circuits (2022)
Keyphrases
- power consumption
- nm technology
- cmos technology
- delta sigma
- analog to digital converter
- low power
- high speed
- mixed signal
- noise shaping
- image sensor
- power dissipation
- clock frequency
- low voltage
- cmos image sensor
- single chip
- real time
- high frequency
- silicon on insulator
- digital signal processing
- image compression
- image processing