Liangjian Lyu

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 17

Top Topics

Top Venues

IEEE Trans. Biomed. Circuits Syst.

Publications

Heyu Ren, Liangjian Lyu, Binbin Chen, Chuanjin Richard Shi
A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR. CICC (2024)
Jingsen Yang, Liangjian Lyu, Zirui Dong, Heyu Ren, C.-J. Richard Shi
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction. A-SSCC (2023)
Renze Gan, Liangjian Lyu, C.-J. Richard Shi
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF. ESSCIRC (2023)
Hao Jiang, Jiapei Zheng, Yunzhengmao Wang, Jinshan Zhang, Haozhe Zhu, Liangjian Lyu, Yingping Chen, Chixiao Chen, Qi Liu
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS (2023)
Qingzhen Wang, Wenxian Gu, Hengchang Bi, Liangjian Lyu, Deli Qiao, Xing Wu
A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces. ASICON (2023)
Haohan Wangxu, Liangjian Lyu, Hengchang Bi, Xing Wu
Flexible Pressure Sensor Array with Multi-Channel Wireless Readout Chip. Sensors 22 (10) (2022)
Renze Gan, Liangjian Lyu, Geng Mu, C.-J. Richard Shi
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. CICC (2022)
Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, C.-J. Richard Shi
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC (2021)
Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, C.-J. Richard Shi
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS (2020)
Liangjian Lyu, Dawei Ye, C.-J. Richard Shi
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 14 (4) (2020)
Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. 70 (2020)
Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, C.-J. Richard Shi
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits 55 (5) (2020)
Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, C.-J. Richard Shi
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs (5) (2020)
Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC (2019)
Dawei Ye, Rongjin Xu, Liangjian Lyu, C.-J. Richard Shi
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS (2019)
Liangjian Lyu, Dawei Ye, C.-J. Richard Shi
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS (2019)
Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, C.-J. Richard Shi
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC (2018)