Dawei Ye

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 18

Top Topics

Metal Oxide Semiconductor

Top Venues

IEEE J. Solid State Circuits

Publications

Dawei Ye, Bingxin Cao, Weiping Zhou
Echo State Network-Enabled Intelligent Smart Sensor Design for Creating a Robotic Nervous System. Int. J. Pattern Recognit. Artif. Intell. 37 (7) (2023)
Rongjin Xu, Dawei Ye, Sirou Li, C.-J. Richard Shi
65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. ISSCC (2022)
Rongjin Xu, Dawei Ye, C.-J. Richard Shi
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Integr. 84 (2022)
Rongjin Xu, Dawei Ye, C.-J. Richard Shi
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". IEEE J. Solid State Circuits 57 (2) (2022)
Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, C.-J. Richard Shi
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC (2021)
Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, C.-J. Richard Shi
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. A-SSCC (2021)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. IEEE J. Solid State Circuits 56 (11) (2021)
Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, C.-J. Richard Shi
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS (2020)
Liangjian Lyu, Dawei Ye, C.-J. Richard Shi
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 14 (4) (2020)
Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, C.-J. Richard Shi
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits 55 (5) (2020)
Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, C.-J. Richard Shi
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs (5) (2020)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. ISSCC (2019)
Dawei Ye, Rongjin Xu, Liangjian Lyu, C.-J. Richard Shi
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS (2019)
Liangjian Lyu, Dawei Ye, C.-J. Richard Shi
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS (2019)
Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, C.-J. Richard Shi
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC (2018)
Dawei Ye, Ronan A. R. van der Zee, Bram Nauta
26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience. ISSCC (2016)
Dawei Ye, Ronan A. R. van der Zee, Bram Nauta
A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance. IEEE J. Solid State Circuits 51 (12) (2016)
Dawei Ye, Ping Lu, Pietro Andreani, Ronan A. R. van der Zee
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. ISCAS (2013)
Ying Wu, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu, Dejan Radjen, Henrik Sjöland
A 0.13µm CMOS ΔΣ PLL FM transmitter. NORCHIP (2011)