Ping Lu

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 4

Top Topics

Metal Oxide Semiconductor

Data Conversion

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Ying Wu, Ping Lu, Robert Bogdan Staszewski
-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2020)
Ying Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise. IEEE J. Solid State Circuits 52 (7) (2017)
Ping Lu, Ying Wu, Pietro Andreani
A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration. IEEE Trans. Circuits Syst. II Express Briefs (11) (2016)
Ying Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. ESSCIRC (2016)
Ahmed Mahmoud, Pietro Andreani, Ping Lu
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise. NORCAS (2015)
Ping Lu, Pietro Andreani
-order noise shaping. ISCAS (2014)
Ji Wang, Manuel Bejarano Carmona, Helgi Hall, Dejan Radjen, Ping Lu
A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio. NORCHIP (2014)
Dawei Ye, Ping Lu, Pietro Andreani, Ronan A. R. van der Zee
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. ISCAS (2013)
Ping Lu, Pietro Andreani, Antonio Liscidini
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter. NORCHIP (2012)
Ping Lu, Antonio Liscidini, Pietro Andreani
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps. IEEE J. Solid State Circuits 47 (7) (2012)
Ping Lu, Ying Wu, Pietro Andreani
A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter. ISCAS (2012)
Ping Lu, Pietro Andreani, Antonio Liscidini
A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs. ESSCIRC (2011)
Ying Wu, Ping Lu, Pietro Andreani
A digital PLL with a multi-delay coarse-fine TDC. NORCHIP (2011)
Muhammad Shakir, Mohammed Abdulaziz, Ping Lu, Pietro Andreani
A mixed mode design flow for multi GHz ADPLLs. NORCHIP (2011)
Ying Wu, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu, Dejan Radjen, Henrik Sjöland
A 0.13µm CMOS ΔΣ PLL FM transmitter. NORCHIP (2011)
Mohammed Abdulaziz, Muhammad Shakir, Ping Lu, Pietro Andreani
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS. NORCHIP (2011)