Yarui Peng

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 12

Top Topics

Ultra Low Power

Human Cerebral Cortex

Design Methodologies

Automatic Extraction

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, Xiaohang Wang
Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test 39 (6) (2022)
M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design. ACM Great Lakes Symposium on VLSI (2021)
M. D. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho, Yarui Peng
Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization. VLSI-DAT (2021)
Imam Al Razi, Quang Le, H. Alan Mantooth, Yarui Peng
Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation. ICCAD (2021)
M. D. Arafat Kabir, Yarui Peng
Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools. ASP-DAC (2020)
M. D. Arafat Kabir, Yarui Peng
Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study. SoCC (2020)
M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design. ICCAD (2020)
Moongon Jung, Taigon Song, Yarui Peng, Sung Kyu Lim
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. ICCAD (2015)
Yarui Peng, Bon Woong Ku, Youn-Sik Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Sung Kyu Lim
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM. DAC (2015)
Yarui Peng, Dusan Petranovic, Sung Kyu Lim
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Yarui Peng, Dusan Petranovic, Sung Kyu Lim
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling. DAC (2014)
Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, Sung Kyu Lim
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. DAC (2014)
Sandeep Kumar Samal, Yarui Peng, Yang Zhang, Sung Kyu Lim
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs. ISLPED (2013)
Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. ICCAD (2013)
Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. DAC (2013)
Yarui Peng, Wenhua Hou
A Framework of Total Performance Improvement and Transaction Cost-driven Business Process Outsourcing Strategy. PACIS (2004)