A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS.
Haozhe ZhuChixiao ChenShiwei LiuQiaosha ZouMingyu WangLihua ZhangXiaoyang ZengC.-J. Richard ShiPublished in: IEEE J. Emerg. Sel. Topics Circuits Syst. (2020)
Keyphrases
- learning algorithm
- detection algorithm
- segmentation algorithm
- memory usage
- memory requirements
- computational complexity
- preprocessing
- search space
- parallel implementation
- feature selection
- analog vlsi
- memory space
- expectation maximization
- dynamic programming
- objective function
- high speed
- probabilistic model
- k means
- optimal solution