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A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder.

Mengjie LiHongyi ZhangSiqi HeHaozhe ZhuHao ZhangJinglei LiuJiayuan ChenZhenping HuXiaoyang ZengChixiao Chen
Published in: ISCAS (2024)
Keyphrases
  • floating point
  • instruction set
  • floating point arithmetic
  • fixed point
  • square root
  • fast fourier transform
  • computer integrated manufacturing
  • sparse matrices
  • data flow
  • worst case
  • floating point unit