Mohammad Shihabul Haque

Publication Activity (10 Years)

Years Active: 2009-2020
Publications (10 Years): 4

Top Topics

Design Space Exploration

Embedded Processors

Top Venues

Publications

Mohammad Shihabul Haque, Daniel Jun Xian Ng, Arvind Easwaran, Karthik Thangamariappan
Contract-based Hierarchical Resilience Management for Cyber-Physical Systems. CoRR (2020)
Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, Y. C. Tay
A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems. ISORC (2018)
Mohammad Shihabul Haque, Daniel Jun Xian Ng, Arvind Easwaran, Karthikeyan Thangamariappan
Contract-Based Hierarchical Resilience Management for Cyber-Physical Systems. Computer 51 (11) (2018)
Mohammad Shihabul Haque, Arvind Easwaran
Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei
Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems. CoRR (2015)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy. CoRR (2015)
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique. CoRR (2015)
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs. CoRR (2015)
Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei
Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems. ASP-DAC (2015)
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. ASP-DAC (2013)
Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS (2012)
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. ICCAD (2011)
Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran
Rapid runtime estimation methods for pipelined MPSoCs. DATE (2010)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC (2010)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE (2010)
Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. CODES+ISSS (2009)