Swarnalatha Radhakrishnan

Publication Activity (10 Years)

Years Active: 2004-2015
Publications (10 Years): 0

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CoRR

VLSI Design

CODES+ISSS

DATE

University of New South Wales, Sydney, Australia (PHD)

Education History

University of New South Wales, Sydney, Australia

PHD

Publications

Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Rajitha Navarathna, Swarnalatha Radhakrishnan, Roshan G. Ragel
Loop Unrolling in Multi-pipeline ASIP Design. CoRR (2014)
B. A. N. M. Bambarasinghe, H. M. S. Huruggamuwa, Roshan G. Ragel, Swarnalatha Radhakrishnan
Axis2UNO: Web Services Enabled Openoffice.org. CoRR (2014)
Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose
Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study. CoRR (2014)
Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran
A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. VLSI Design (2013)
Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. DATE (2013)
Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI (2013)
Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS (2012)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Comput. Digit. Tech. 3 (1) (2009)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Customization of application specific heterogeneous multi-pipeline processors. DATE (2006)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS (2006)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Dual-pipeline heterogeneous ASIP design. CODES+ISSS (2004)

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Publication Activity (10 Years)

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Swarnalatha Radhakrishnan