Jorgen Peddersen

Publication Activity (10 Years)

Years Active: 2005-2020
Publications (10 Years): 7

Top Topics

Replacement Policy

Dependency Graph

Top Venues

Publications

Vikkitharan Gnanasambandapillai, Jorgen Peddersen, Roshan G. Ragel, Sri Parameswaran
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (11) (2020)
Josef Schneider, Jorgen Peddersen, Sri Parameswaran
Speeding up single pass simulation of PLRUt caches. ASP-DAC (2015)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy. CoRR (2015)
Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran
RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. ICCD (2015)
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique. CoRR (2015)
Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. ICCD (2015)
Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran
E-pipeline: elastic hardware/software pipelines on a many-core fabric. DATE (2015)
Josef Schneider, Jorgen Peddersen, Sri Parameswaran
MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. DAC (2014)
Josef Schneider, Jorgen Peddersen, Sri Parameswaran
A scorchingly fast FPGA-based Precise L1 LRU cache simulator. ASP-DAC (2014)
Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. ASP-DAC (2014)
Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI (2013)
Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. ISVLSI (2013)
Liang Tang, Jorgen Peddersen, Sri Parameswaran
A Rapid Methodology for Multi-mode Communication Circuit Generation. VLSI Design (2012)
Su Myat Min, Jorgen Peddersen, Sri Parameswaran
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. VLSI Design (2011)
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. ICCAD (2011)
Xin He, Jorgen Peddersen, Sri Parameswaran
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. Des. Autom. Embed. Syst. 14 (3) (2010)
Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. DATE (2010)
Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. DIPES/BICC (2010)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC (2010)
Karin Avnit, Arcot Sowmya, Jorgen Peddersen
ACS: Automatic Converter Synthesis for SoC Bus Protocols. TACAS (2010)
Xin He, Jorgen Peddersen, Sri Parameswaran
Improved Architectures for Range Encoding in Packet Classification System. NCA (2010)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE (2010)
Xin He, Jorgen Peddersen, Sri Parameswaran
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. CODES+ISSS (2009)
Xin He, Jorgen Peddersen, Sri Parameswaran
LOP_RE: Range encoding for low power packet classification. LCN (2009)
Jorgen Peddersen, Sri Parameswaran
Low-Impact Processor for Dynamic Runtime Power Management. IEEE Des. Test Comput. 25 (1) (2008)
Jorgen Peddersen, Sri Parameswaran
Energy Driven Application Self-Adaptation at Run-time. J. Comput. 3 (3) (2008)
Jorgen Peddersen, Sri Parameswaran
Energy Driven Application SelfAdaptation. VLSI Design (2007)
Jorgen Peddersen, Sri Parameswaran
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. ASP-DAC (2007)
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran
Rapid Embedded Hardware/Software System Generation. VLSI Design (2005)