A scorchingly fast FPGA-based Precise L1 LRU cache simulator.
Josef SchneiderJorgen PeddersenSri ParameswaranPublished in: ASP-DAC (2014)
Keyphrases
- hit rate
- cache management
- prefetching
- replacement policy
- hit ratio
- cache replacement algorithm
- miss ratio
- access patterns
- memory management
- response time
- distributed object
- hardware implementation
- garbage collection
- data access
- hardware design
- hardware architecture
- simulation model
- test bed
- main memory
- buffer pool
- query processing
- web caching
- low cost