Andhi Janapsatya

Publication Activity (10 Years)

Years Active: 2004-2015
Publications (10 Years): 0

Top Venues

CoRR

University of New South Wales, Sydney, Australia (PHD)

Education History

University of New South Wales, Sydney, Australia

PHD

Publications

Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy. CoRR (2015)
Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran
Rapid runtime estimation methods for pipelined MPSoCs. DATE (2010)
Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. DATE (2010)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC (2010)
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE (2010)
Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. CODES+ISSS (2009)
Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic
HitME: low power Hit MEmory buffer for embedded systems. ASP-DAC (2009)
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel
Instruction trace compression for rapid instruction cache simulation. DATE (2007)
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
Finding optimal L1 cache configuration for embedded systems. ASP-DAC (2006)
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
A novel instruction scratchpad memory optimization method based on concomitance metric. ASP-DAC (2006)
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. IEEE Trans. Very Large Scale Integr. Syst. 14 (8) (2006)
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran
Rapid Embedded Hardware/Software System Generation. VLSI Design (2005)
Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic
Hardware/software managed scratchpad memory for embedded system. ICCAD (2004)

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Publication Activity (10 Years)

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Andhi Janapsatya