Kewal K. Saluja

Publication Activity (10 Years)

Years Active: 1972-2021
Publications (10 Years): 18

Top Venues

VLSI Design

J. Electron. Test.

ISVLSI

IEICE Trans. Inf. Syst.

Publications

Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method. J. Electron. Test. 37 (3) (2021)
Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
Fault Tolerance through Invariant Checking for the Lanczos Eigensolver. VLSI Design (2020)
Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
Fault Tolerant Cholesky Factorization on GPUs. FTXS@SC (2018)
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. IEICE Trans. Inf. Syst. (9) (2017)
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
Identifying high variability speed-limiting paths under aging. LATS (2017)
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. 33 (6) (2017)
Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja
Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC (2017)
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model. ACM Trans. Embed. Comput. Syst. 15 (3) (2016)
Parameswaran Ramanathan, Kewal K. Saluja
Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations. ATS (2016)
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. IPSJ Trans. Syst. LSI Des. Methodol. 9 (2016)
Kewal K. Saluja
Digital Testing - Basics to Advanced Research Issues. VLSI Design (2016)
Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
Fault Tolerance through Invariant Checking for Iterative Solvers. VLSI Design (2016)
Rehan Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, Parameswaran Ramanathan, Kewal K. Saluja
Thermal Extension of the Total Bandwidth Server. VLSI Design (2015)
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Diagnosis of Delay Faults Considering Hazards. ISVLSI (2015)
Spencer K. Millican, Kewal K. Saluja
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints. VLSI Design (2015)
Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja
Privacy Assurance in Data-Aggregation for Multiple MAX Transactions. COMPSAC Workshops (2015)
Felix Loh, Parameswaran Ramanathan, Kewal K. Saluja
Transient Fault Resilient QR Factorization on GPUs. FTXS@HPDC (2015)
Virendra Singh, Adit D. Singh, Kewal K. Saluja
A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS (2015)
Spencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities. VLSI Design (2014)
Spencer K. Millican, Kewal K. Saluja
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits. VLSI Design (2014)
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
Temperature Minimization Using Power Redistribution in Embedded Systems. VLSI Design (2014)
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. ISVLSI (2014)
Spencer K. Millican, Kewal K. Saluja
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling. J. Electron. Test. 30 (5) (2014)
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks. ECRTS (2014)
Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. Asian Test Symposium (2013)
Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja
Privacy Assurances in Multiple Data-Aggregation Transactions. ICISC (2013)
Spencer K. Millican, Kewal K. Saluja
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling. Asian Test Symposium (2013)
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao
Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems. VLSI Design (2013)
Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI (2013)
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
On thermal utilization of periodic task sets in uni-processor systems. RTCSA (2013)
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment. IEICE Trans. Inf. Syst. (6) (2013)
Warin Sootkaneung, Kewal K. Saluja
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate. VLSI Design (2012)
Spencer K. Millican, Kewal K. Saluja
Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits. Asian Test Symposium (2012)
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Diagnosis for Bridging Faults on Clock Lines. PRDC (2012)
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
On Detecting Transition Faults in the Presence of Clock Delay Faults. Asian Test Symposium (2011)
Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja
A low cost approach to calibrate on-chip thermal sensors. ISQED (2011)
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Fault simulation and test generation for clock delay faults. ASP-DAC (2011)
Yen-Ting Lin, Kewal K. Saluja, Seapahn Megerian
Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors. Ad Hoc Networks 9 (5) (2011)
Chin-Ya Huang, Parameswaran Ramanathan, Kewal K. Saluja
Routing TCP Flows in Underwater Mesh Networks. IEEE J. Sel. Areas Commun. 29 (10) (2011)
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
Temperature Dependent Test Scheduling for Multi-core System-on-Chip. Asian Test Symposium (2011)
Tsuyoshi Iwagaki, Kewal K. Saluja
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. DDECS (2011)
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. VLSI Design (2011)
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Enhancement of Clock Delay Faults Testing. ETS (2011)
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
SEU tolerant SRAM cell. ISQED (2011)
Chunhua Yao, Kewal K. Saluja, Parmesh Ramanathan
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach. J. Electron. Test. 27 (6) (2011)
Warin Sootkaneung, Kewal K. Saluja
Soft error reduction through gate input dependent weighted sizing in combinational circuits. ISQED (2011)
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. ICCD (2011)
Hiroshi Yokoyama, Hideo Tamamoto, Kewal K. Saluja
Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST. Asian Test Symposium (2010)
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh
On Minimization of Test Application Time for RAS. VLSI Design (2010)
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
Energy-efficient redundant execution for chip multiprocessors. ACM Great Lakes Symposium on VLSI (2010)
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. DATE (2010)
Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
Collaborative patrolling for target detection using mobile sensor networks. WCSP (2010)
Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja
Modeling latency - lifetime trade-off for target detection in mobile sensor networks. ACM Trans. Sens. Networks 7 (1) (2010)
Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Yen-Ting Lin, Kewal K. Saluja, Parameswaran Ramanathan
Connected Barrier Coverage on a Narrow Band: Analysis and Deployment. SECON (2010)
Lin Xie, Azadeh Davoodi, Kewal K. Saluja
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. DAC (2010)
Warin Sootkaneung, Kewal K. Saluja
On techniques for handling soft errors in digital circuits. ITC (2010)
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh
Modified T-Flip-Flop based scan cell for RAS. ETS (2010)
Warin Sootkaneung, Kewal K. Saluja
Gate input reconfiguration for combating soft errors in combinational circuits. DSN Workshops (2010)
Ho-Yong Choi, Kewal K. Saluja
Detection of inter-port bridging faults in dual-port memories. ISCAS (2010)
A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh
Test application time minimization for RAS using basis optimization of column decoder. ISCAS (2010)
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. DSN (2010)
Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
SEU tolerant SRAM for FPGA applications. FPT (2010)
Chao Wang, Parmesh Ramanathan, Kewal K. Saluja
Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions. SECON (2009)
Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja
DX-compactor: distributed X-compaction for SoCs. ACM Great Lakes Symposium on VLSI (2009)
Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. VLSI Design (2009)
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
Power and thermal constrained test scheduling. ITC (2009)
Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
Modeling Detection Latency with Collaborative Mobile Sensing Architecture. IEEE Trans. Computers 58 (5) (2009)
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Kyuchull Kim, Kewal K. Saluja
Low-Area Wrapper Cell Design for Hierarchical SoC Testing. J. Electron. Test. 25 (6) (2009)
Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar
False Path Aware Timing Yield Estimation under Variability. VTS (2009)
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. Asian Test Symposium (2009)
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Mohammad Gh. Mohammad, Kewal K. Saluja
Analysis and test procedures for NOR flash memory defects. Microelectron. Reliab. 48 (5) (2008)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24 (4) (2008)
Mohammad Gh. Mohammad, Kewal K. Saluja
Testing Flash Memories for Tunnel Oxide Defects. VLSI Design (2008)
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS (2008)
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang
NBTI Degradation: A Problem or a Scare? VLSI Design (2008)
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
An accurate flip-flop selection technique for reducing logic SER. DSN (2008)
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. ATS (2008)
Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja
Moments Based Blind Calibration in Mobile Sensor Networks. ICC (2008)
Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan
Implementing high availability memory with a duplication cache. MICRO (2008)
Chao Wang, Parmesh Ramanathan, Kewal K. Saluja
Calibrating Nonlinear Mobile Sensors. SECON (2008)
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Trans. Inf. Syst. (3) (2008)
Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. (1) (2007)
Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja
On NBTI Degradation Process in Digital Logic Circuits. VLSI Design (2007)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC (2007)
Xiangning Yang, Kewal K. Saluja
Combating NBTI Degradation via Gate Sizing. ISQED (2007)
Kim T. Le, Dong Hyun Baik, Kewal K. Saluja
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. VLSI Design (2007)
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design (2007)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. (9) (2007)
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. ATS (2007)
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. IEEE Trans. Very Large Scale Integr. Syst. 15 (7) (2007)
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. IEICE Trans. Inf. Syst. (3) (2006)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD (2006)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
-Fault Model. IEICE Trans. Inf. Syst. (11) (2006)
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. ATS (2006)
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
Energy Estimation of the Memory Subsystem in Multiprocessor Systems. J. Low Power Electron. 2 (3) (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Kewal K. Saluja