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Dong Hyun Baik
Publication Activity (10 Years)
Years Active: 2003-2007
Publications (10 Years): 0
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Publications
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Kim T. Le
,
Dong Hyun Baik
,
Kewal K. Saluja
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.
VLSI Design
(2007)
Dong Hyun Baik
,
Kewal K. Saluja
Test Cost Reduction Using Partitioned Grid Random Access Scan.
VLSI Design
(2006)
Jeng-Liang Tsai
,
Dong Hyun Baik
,
Charlie Chung-Ping Chen
,
Kewal K. Saluja
Yield-Driven, False-Path-Aware Clock Skew Scheduling.
IEEE Des. Test Comput.
22 (3) (2005)
Dong Hyun Baik
,
Kewal K. Saluja
Progressive random access scan: a simultaneous solution to test power, test data volume and test time.
ITC
(2005)
Dong Hyun Baik
,
Kewal K. Saluja
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.
Asian Test Symposium
(2005)
Jeng-Liang Tsai
,
Dong Hyun Baik
,
Charlie Chung-Ping Chen
,
Kewal K. Saluja
False Path and Clock Scheduling Based Yield-Aware Gate Sizing.
VLSI Design
(2005)
Jeng-Liang Tsai
,
Dong Hyun Baik
,
Charlie Chung-Ping Chen
,
Kewal K. Saluja
A yield improvement methodology using pre- and post-silicon statistical clock scheduling.
ICCAD
(2004)
Dong Hyun Baik
,
Kewal K. Saluja
,
Seiji Kajihara
Random Access Scan: A solution to test power, test data volume and test time.
VLSI Design
(2004)
Vishwani D. Agrawal
,
Dong Hyun Baik
,
Yong Chang Kim
,
Kewal K. Saluja
Exclusive Test and its Applications to Fault Diagnosis.
VLSI Design
(2003)