Charlie Chung-Ping Chen

Publication Activity (10 Years)

Years Active: 2000-2022
Publications (10 Years): 11

Top Topics

Dc Dc Converter

Design Automation

Tracking Scheme

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen
Intelligent Design Automation for Heterogeneous Integration. ISPD (2022)
Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen
Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. DATE (2021)
Chung-Yi Ting, Jing-Yuan Lin, Charlie Chung-Ping Chen
Hysteretic Buck Converter With Adaptive COT Control for Fast DVS and Load-Transient Response in RF Applications. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Yi-Chieh Hsu, Chung-Yi Ting, Li-Sheng Hsu, Jing-Yuan Lin, Charlie Chung-Ping Chen
A Transient Enhancement DC-DC Buck Converter With Dual Operating Modes Control Technique. IEEE Trans. Circuits Syst. II Express Briefs (8) (2019)
Shuo-Hong Hung, Ina Wu, Yi-Chen Li, Cheng-Ta Li, Charlie Chung-Ping Chen
A Real Time EEG Analysis System for the Prediction of Clinical Antidepressant Responses. DSL (2018)
Pei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang, Charlie Chung-Ping Chen
Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system. DATE (2016)
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. IEEE J. Solid State Circuits 51 (2) (2016)
Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme. ISCAS (2015)
Kuan-I Wu, I-Shing Shen, Christina F. Jou, Charlie Chung-Ping Chen
A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique. VLSIC (2015)
Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen
A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. ISCAS (2015)
Kuan-I Wu, Szu-Yao Hung, Shuo-Hong Hung, Charlie Chung-Ping Chen
A fast-settling high linearity auto gain control for broadband OFDM-based PLC system. ISCAS (2015)
Kuan-I Wu, Shuo-Hong Hung, Shang-Yu Shieh, Bor-Tsang Hwang, Szu-Yao Hung, Charlie Chung-Ping Chen
Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation. ISCAS (2014)
Chun-Chang Yu, Chia-Hao Cheng, Pei-Chun Lin, Charlie Chung-Ping Chen
Cost-efficient hardware implementation of stereo image depth optimization system. IC3D (2014)
Shih-Lun Huang, Sheng-Yi Hung, Charlie Chung-Ping Chen, Cheng-Han Tsao, Nai-Wen Chang
An efficient multi-touch tracking algorithm with a large number of points. ICCE-Berlin (2014)
Pang-Kai Liu, Szu-Yao Hung, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology. ISCAS (2013)
Szu-Yao Hung, Kai-Hsiang Chan, Charlie Chung-Ping Chen
A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system. ISCAS (2013)
Wei-Sheng Cheng, Min-Han Hsieh, Shuo-Hong Hung, Szu-Yao Hung, Charlie Chung-Ping Chen
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS. ISCAS (2013)
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
fast-locking all-digital DLL in 90nm CMOS. ISSCC (2012)
Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen
A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm. ISCAS (2012)
Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu
Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen
A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique. ISCAS (2011)
Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen
An at-speed self-testable technique for the high speed domino adder. CICC (2011)
Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin, Charlie Chung-Ping Chen
A 12 Gb/s chip-to-chip AC coupled transceiver. ISCAS (2011)
Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen
Accurate and Analytical Statistical Spatial Correlation Modeling Based on Singular Value Decomposition for VLSI DFM Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (4) (2010)
Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. ASP-DAC (2010)
Dongkeun Oh, Charlie Chung-Ping Chen, Nam Sung Kim, Yu Hen Hu
The compatibility analysis of thread migration and DVFS in multi-core processor. ISQED (2010)
Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen
Process-Variation Statistical Modeling for VLSI Timing Analysis. ISQED (2008)
Tuck Boon Chan, Hsinchia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen
LTCC spiral inductor modeling, synthesis, and optimization. ASP-DAC (2008)
Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng
An optimal algorithm for sizing sequential circuits for industrial library based designs. ASP-DAC (2008)
Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen
Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. DAC (2008)
Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu
Numerically Convex Forms and Their Application in Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
Sanghamitra Roy, Charlie Chung-Ping Chen
SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. ASP-DAC (2007)
Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. ISQED (2007)
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
Statistical timing analysis with path reconvergence and spatial correlations. DATE (2006)
Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ASP-DAC (2006)
Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen
Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. ISCAS (2006)
Lizheng Zhang, Jun Shao, Charlie Chung-Ping Chen
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. ISPD (2006)
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar
Temperature-Aware Placement for SOCs. Proc. IEEE 94 (8) (2006)
Sanghamitra Roy, Charlie Chung-Ping Chen
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. ISQED (2006)
Jeng-Liang Tsai, Charlie Chung-Ping Chen
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC (2005)
Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li
System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). ICCAD (2005)
Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. DAC (2005)
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
Wave-pipelined on-chip global interconnect. ASP-DAC (2005)
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Des. Test Comput. 22 (3) (2005)
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. DATE (2005)
Rong Jiang, Charlie Chung-Ping Chen
Comprehensive frequency dependent interconnect extraction and evaluation methodology. ASP-DAC (2005)
Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (6) (2005)
Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (10) (2005)
Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. DAC (2005)
Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. ASP-DAC (2005)
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
Block based statistical timing analysis with extended canonical timing model. ASP-DAC (2005)
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design (2005)
Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. ICCAD (2005)
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
Thermal and Power Integrity Based Power/Ground Networks Optimization. DATE (2004)
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
Sensitivity guided net weighting for placement driven synthesis. ISPD (2004)
Rong Jiang, Charlie Chung-Ping Chen
Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. DATE (2004)
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Rong Jiang, Charlie Chung-Ping Chen
SCORE: SPICE COmpatible Reluctance Extraction. DATE (2004)
Ting-Yuan Wang, Charlie Chung-Ping Chen
SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. ISQED (2004)
Clement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen
Frequency-dependent reluctance extraction. ASP-DAC (2004)
Rong Jiang, Charlie Chung-Ping Chen
EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents. CICC (2004)
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD (2004)
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. DAC (2004)
Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen
3D thermal-ADI: an efficient chip-level transient thermal simulator. ISPD (2003)
Yu-Min Lee, Charlie Chung-Ping Chen
A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. ASP-DAC (2003)
Rong Jiang, Tsung-Hao Chen, Charlie Chung-Ping Chen
PODEA: Power delivery efficient analysis with realizable model reduction. ISCAS (4) (2003)
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
INDUCTWISE: inductance-wise interconnect simulator and extractor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (7) (2003)
Yu-Min Lee, Charlie Chung-Ping Chen
The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (11) (2003)
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. ICCAD (2003)
Yu-Min Lee, Charlie Chung-Ping Chen
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . DATE (2003)
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ISPD (2003)
Ting-Yuan Wang, Charlie Chung-Ping Chen
Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method. IEEE Trans. Very Large Scale Integr. Syst. 11 (4) (2003)
Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. DAC (2002)
Ting-Yuan Wang, Charlie Chung-Ping Chen
3-D Thermal-ADI: a linear-time chip level transient thermal simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (12) (2002)
Ting-Yuan Wang, Charlie Chung-Ping Chen
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. ISQED (2002)
Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen
INDUCTWISE: inductance-wise interconnect simulator and extractor. ICCAD (2002)
Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. VLSI Design 2002 (3) (2002)
Charlie Chung-Ping Chen, Ed Cheng
Future SoC Design Challenges and Solutions (invited). ISQED (2002)
Yu-Min Lee, Charlie Chung-Ping Chen
Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (11) (2002)
Tsung-Hao Chen, Charlie Chung-Ping Chen
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. DAC (2001)
Ting-Yuan Wang, Charlie Chung-Ping Chen
Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. ISPD (2001)
Yu-Min Lee, Charlie Chung-Ping Chen
Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method. ICCAD (2001)
Pradeepsunder Ganesh, Charlie Chung-Ping Chen
RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. ICCD (2001)
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
Optimal spacing and capacitance padding for general clock structures. ASP-DAC (2001)
Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen
Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. ICCD (2001)
Yu-Min Lee, Charlie Chung-Ping Chen
Hierarchical model order reduction for signal-integrity interconnect synthesis. ACM Great Lakes Symposium on VLSI (2001)
Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness
Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. ICCAD (2000)