An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
Yu-Shun WangMin-Han HsiehJames Chien-Mo LiCharlie Chung-Ping ChenPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2012)
Keyphrases
- high order
- high speed
- bit parallel
- low power
- higher order
- logic circuits
- power dissipation
- data flow
- pairwise
- low order
- markov random field
- real time
- feature extraction
- lower order
- context modeling
- zernike moments
- multiscale
- multi task learning
- statistical tests
- maximum entropy
- partial differential equations
- event detection
- basis functions
- bayesian logistic regression