Min-Han Hsieh

Publication Activity (10 Years)

Years Active: 2011-2016
Publications (10 Years): 1

Top Topics

Cmos Technology

Impact Analysis

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. IEEE J. Solid State Circuits 51 (2) (2016)
Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme. ISCAS (2015)
Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen
A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. ISCAS (2015)
Pang-Kai Liu, Szu-Yao Hung, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology. ISCAS (2013)
Li Wang, Chun-Jui Yeh, Min-Han Hsieh, Cheng-Tai Wu, Chieh-Lung Lu
System-impact analysis of a large-scale offshore wind farm connected to Taiwan power system. IAS (2013)
Wei-Sheng Cheng, Min-Han Hsieh, Shuo-Hong Hung, Szu-Yao Hung, Charlie Chung-Ping Chen
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS. ISCAS (2013)
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
fast-locking all-digital DLL in 90nm CMOS. ISSCC (2012)
Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen
A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm. ISCAS (2012)
Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen
A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique. ISCAS (2011)
Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen
An at-speed self-testable technique for the high speed domino adder. CICC (2011)
Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin, Charlie Chung-Ping Chen
A 12 Gb/s chip-to-chip AC coupled transceiver. ISCAS (2011)