Shen-Iuan Liu

ORCID

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 49

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Very Large Scale Integr. Syst.

A-SSCC

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yi-Hao Lan, Shen-Iuan Liu
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. IEEE Trans. Very Large Scale Integr. Syst. 32 (4) (2024)
Hsi-Kai Peng, Shen-Iuan Liu
A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection. IEEE Trans. Very Large Scale Integr. Syst. 32 (4) (2024)
Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. IEEE Trans. Very Large Scale Integr. Syst. 32 (3) (2024)
Jhe-En Lin, Yi-Hao Lan, Shen-Iuan Liu
A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker. IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Yi-Hao Lan, Shen-Iuan Liu
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32 (7) (2024)
Zhi-Heng Kang, Shen-Iuan Liu
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation. IEEE J. Solid State Circuits 58 (3) (2023)
Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu
A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su, Shen-Iuan Liu
An Adaptive Digital PLL Based on BBPFD Transition Probability. VLSI-DAT (2022)
Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu
A Wide-Range FD for Referenceless Baud-Rate CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs 69 (1) (2022)
Jia-Rong Chang, Shen-Iuan Liu
A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu
An Injection-Locked Clock Multiplier With Injection Strength Calibration. VLSI-DAT (2022)
Wen-Chi Huang, Shen-Iuan Liu
A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit. IEEE Trans. Circuits Syst. II Express Briefs 69 (12) (2022)
Yao-Hung Tsai, Shen-Iuan Liu
12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 30 (7) (2022)
Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Shun-Chi Chang, Shen-Iuan Liu
A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu
A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu
A Digital Phase-Locked Loop With Background Supply Noise Cancellation. VLSI-DAT (2021)
Ming-Han Chou, Shen-Iuan Liu
A Type-I PLL With Foreground Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu
A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (11) (2021)
Guan-Yu Su, Zhi-Heng Kang, Shen-Iuan Liu
An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique. VLSI-DAT (2021)
Yong-Ru Lu, Shen-Iuan Liu, Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, Ying-Hsi Lin
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68 (3) (2021)
Guan-Yu Su, Shen-Iuan Liu
A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Chung-Jen Kuo, Shen-Iuan Liu
A 13.56 MHz Current-Mode Wireless Power Receiver With Energy-Investment Capability. IEEE Trans. Circuits Syst. II Express Briefs (2) (2020)
Kuan-Lin Fu, Shen-Iuan Liu
A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration. IEEE Trans. Very Large Scale Integr. Syst. 28 (7) (2020)
Ming-Chia Chang, Min-Hsuan Wu, Shen-Iuan Liu
A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT. VLSI-DAT (2020)
Ming-Han Chou, Shen-Iuan Liu
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL. IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Ming-Chia Chang, Shen-Iuan Liu
An Indoor Photovoltaic Energy Harvester Using Time-Based MPPT and On-Chip Photovoltaic Cell. IEEE Trans. Circuits Syst. (11) (2020)
Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu
A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time. A-SSCC (2019)
Che-Wei Tien, Shen-Iuan Liu
A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Yu-Kai Chiu, Shen-Iuan Liu
A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor. IEEE Trans. Very Large Scale Integr. Syst. 27 (11) (2019)
Cheng-En Hsieh, Shen-Iuan Liu
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu
An On-Chip Relaxation Oscillator With Comparator Delay Compensation. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Yi-An Chang, Shen-Iuan Liu
A 13.4-MHz Relaxation Oscillator With Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. 27 (7) (2019)
Ye-Sing Luo, Hsing-Hung Lin, Shen-Iuan Liu
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control. A-SSCC (2018)
San-Liang Lee, Jyehong Chen, Shen-Iuan Liu, Chang-Fa Yang, Hen-Wai Tsao, Shih-Hsiang Hsu, Chien-Chung Lin, Chun-Liang Yang, Zhong Jie Zhang, Kuan-Lin Fu, Lung Wei Chung, Tomas Pankra
Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect. WOCC (2018)
Che-Wei Tien, Shen-Iuan Liu
A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Wun-Jian Su, Shen-Iuan Liu
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2017)
Ye-Sing Luo, Shen-Iuan Liu
A Voltage Multiplier With Adaptive Threshold Voltage Compensation. IEEE J. Solid State Circuits 52 (8) (2017)
Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu
A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS. IEEE Trans. Circuits Syst. II Express Briefs (11) (2017)
Yen-Hsiang Tseng, Che-Wei Yeh, Shen-Iuan Liu
A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2017)
Kuan-Lin Fu, Shen-Iuan Liu
A 56Gbps PAM-4 optical receiver front-end. A-SSCC (2017)
Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu
A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs. IEEE Trans. Circuits Syst. II Express Briefs (6) (2017)
Liang-Jen Chen, Shen-Iuan Liu
A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Ting-Kuei Kuan, Shen-Iuan Liu
A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques. IEEE J. Solid State Circuits 51 (4) (2016)
Chih-Lu Wei, Shen-Iuan Liu
A Digital PLL Using Oversampling Delta-Sigma TDC. IEEE Trans. Circuits Syst. II Express Briefs (7) (2016)
Chi-Huan Chiang, Chang-Cheng Huang, Ting-Kuei Kuan, Shen-Iuan Liu
A digital MDLL using switched biasing technique to reduce low-frequency phase noise. A-SSCC (2016)
Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu
19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation. ISSCC (2016)
Liang-Jen Chen, Shen-Iuan Liu
A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time. IEEE Trans. Circuits Syst. II Express Briefs (2) (2016)
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. IEEE J. Solid State Circuits 51 (2) (2016)
Ting-Kuei Kuan, Shen-Iuan Liu
A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Chi-Huan Chiang, Chang-Cheng Huang, Shen-Iuan Liu
A digital bang-bang phase-locked loop with bandwidth calibration. A-SSCC (2015)
Kai-Hui Zeng, Ting-Kuei Kuan, Shen-Iuan Liu
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider. IEEE Trans. Circuits Syst. II Express Briefs (11) (2015)
Chih-Lu Wei, Ting-Kuei Kuan, Shen-Iuan Liu
A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth. IEEE Trans. Circuits Syst. II Express Briefs (6) (2015)
Ting-Kuei Kuan, Shen-Iuan Liu
A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction. VLSIC (2015)
Yuan-Fu Lin, Chang-Cheng Huang, Jiunn-Yih Max Lee, Chih-Tien Chang, Shen-Iuan Liu
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting. A-SSCC (2014)
Ye-Sing Luo, Shen-Iuan Liu
A low-input-swing AC-DC voltage multiplier using Schottky diodes. A-SSCC (2014)
I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu
An All-Digital Despreading Clock Generator. IEEE Trans. Circuits Syst. II Express Briefs (1) (2014)
Yu-Hsun Chien, Kuan-Lin Fu, Shen-Iuan Liu
A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Cheng-En Hsieh, Shen-Iuan Liu
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS. A-SSCC (2014)
Yu-Hsuan Chiang, Shen-Iuan Liu
Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient. IEEE Trans. Circuits Syst. II Express Briefs (9) (2014)
Shih-Hsiang Shen, Chung-Yi Ting, Chi-Yun Liu, Hua Cheng, Shen-Iuan Liu, Chih-Ting Lin
A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis. BHI (2014)
Chien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop. A-SSCC (2014)
Ting-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu
A 0.43pJ/bit true random number generator. A-SSCC (2014)
Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu
Ultrasonic telemetry and neural stimulator with FSK-PWM signaling. VLSI-DAT (2013)
Pin-Hao Feng, Shen-Iuan Liu
Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS. IEEE J. Solid State Circuits 48 (2) (2013)
Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu
Ultrasonic Power/Data Telemetry and Neural Stimulator With OOK-PM Signaling. IEEE Trans. Circuits Syst. II Express Briefs (12) (2013)
Shih-Yuan Kao, Shen-Iuan Liu
A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection. IEEE J. Solid State Circuits 48 (11) (2013)
I-Ting Lee, Kai-Hui Zeng, Shen-Iuan Liu
A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB. IEEE Trans. Circuits Syst. II Express Briefs (9) (2013)
Yan-Yu Lin, Shen-Iuan Liu
4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. ISSCC (2013)
Yi-Chieh Huang, Shen-Iuan Liu
A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing. IEEE J. Solid State Circuits 48 (2) (2013)
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Yu-Hsuan Chiang, Shen-Iuan Liu
A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation. IEEE Trans. Circuits Syst. II Express Briefs (12) (2013)
I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu
An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2013)
Shih-Yuan Kao, Shen-Iuan Liu
A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection. IEEE J. Solid State Circuits 48 (2) (2013)
Yan-Yu Lin, Shen-Iuan Liu
4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation. IEEE Trans. Circuits Syst. II Express Briefs (5) (2013)
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
fast-locking all-digital DLL in 90nm CMOS. ISSCC (2012)
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology. IEEE J. Solid State Circuits 47 (11) (2012)
Ke-Hou Chen, Shen-Iuan Liu
Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2012)
Kun-Hung Tsai, Shen-Iuan Liu
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Shen-Iuan Liu, Tsung-Hsien Lin, Woogeun Rhee
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 47 (11) (2012)
I-Ting Lee, Hung-Yu Lu, Shen-Iuan Liu
A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique. IEEE Trans. Circuits Syst. II Express Briefs (5) (2012)
Yi-Chieh Huang, Shen-Iuan Liu
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. ISSCC (2012)
Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs (3) (2012)
I-Ting Lee, Shen-Iuan Liu
G-Band Injection-Locked Frequency Dividers Using π-type LC Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2012)
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
A fast-locking phase-locked loop using CP control and gated VCO. VLSI-DAT (2012)
Yu-Ming Ying, Shen-Iuan Liu
A 20Gb/s digitally adaptive equalizer/DFE with blind sampling. ISSCC (2011)
Shih-Yuan Kao, Shen-Iuan Liu
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. IEEE Trans. Very Large Scale Integr. Syst. 19 (4) (2011)
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
A leakage-current-recycling phase-locked loop in 65nm CMOS technology. A-SSCC (2011)
Bo-Yu Lin, Shen-Iuan Liu
Analysis and Design of D-Band Injection-Locked Frequency Dividers. IEEE J. Solid State Circuits 46 (6) (2011)
I-Ting Lee, Chiao-Hsing Wang, Shen-Iuan Liu
3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS. A-SSCC (2011)
Chang-Lin Hsieh, Shen-Iuan Liu
Decision Feedback Equalizers Using the Back-Gate Feedback Technique. IEEE Trans. Circuits Syst. II Express Briefs (12) (2011)
Yi-Chieh Huang, Shen-Iuan Liu
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization. ISSCC (2011)
Chang-Lin Hsieh, Shen-Iuan Liu
A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector. IEEE Trans. Circuits Syst. II Express Briefs (8) (2011)
Wei-Jen Huang, Shigeisa Nagayasu, Shen-Iuan Liu
A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2011)
Chao-Ching Hung, Shen-Iuan Liu
A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. IEEE Trans. Circuits Syst. II Express Briefs (6) (2011)
Bo-Yu Lin, Shen-Iuan Liu
A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS. IEEE Trans. Circuits Syst. II Express Briefs (10) (2011)
Chao-Ching Hung, Shen-Iuan Liu
A Noise Filtering Technique for Fractional-N Frequency Synthesizers. IEEE Trans. Circuits Syst. II Express Briefs (3) (2011)
Shih-Yuan Kao, Shen-Iuan Liu
A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (5) (2010)
Jung-Yu Chang, Shen-Iuan Liu
A Phase-Locked Loop With Background Leakage Current Compensation. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)

Shen-Iuan Liu.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Shen-Iuan Liu