An On-Chip Relaxation Oscillator With Comparator Delay Compensation.
Yi-An ChangTrio AdionoAmy HamidahShen-Iuan LiuPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2019)
Keyphrases
- power dissipation
- high speed
- low cost
- limit cycle
- phase locked loop
- analog vlsi
- probabilistic relaxation
- differential equations
- iterative algorithms
- single chip
- physical design
- high density
- critical path
- programmable logic
- chip design
- vlsi design
- power consumption
- real time
- vlsi implementation
- lagrangian relaxation
- low power
- lognormal distribution
- phase locked