A leakage-current-recycling phase-locked loop in 65nm CMOS technology.

I-Ting Lee Yun-Ta Tsai Shen-Iuan Liu

Published in: A-SSCC (2011)

Keyphrases

low voltage
leakage current
cmos technology
phase locked loop
low power
power line
power consumption
parallel processing
multipath
random access memory
high voltage
design considerations
power dissipation
power management
image sensor
silicon on insulator
high speed
digital signal processing