A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator.

Jia-Rong Chang Shen-Iuan Liu

Published in: IEEE Trans. Circuits Syst. II Express Briefs (2022)

Keyphrases

error rate
high speed
error analysis
sliding mode control
power system
error bounds
controller design
real time
neural network
database systems
concurrency control
operating conditions
fine granularity
optimal location