Ping-Ying Wang

Publication Activity (10 Years)

Years Active: 2005-2015
Publications (10 Years): 2

Top Topics

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang
A 1V fractional-N PLL with nonlinearity-insensitive modulator. A-SSCC (2015)
Che-Fu Liang, Ping-Ying Wang
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. ISSCC (2015)
Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO. ISSCC (2014)
Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs (3) (2012)
Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng
An all-digital built-in self-test technique for transfer function characterization of RF PLLs. DATE (2011)
Ping-Ying Wang, Chia-Huang Fu
All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL. ESSCIRC (2010)
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. IEEE J. Solid State Circuits 44 (8) (2009)
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. CICC (2008)
Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan
A fractional spur reduction technique for RF TDC-based all digital PLLs. ESSCIRC (2008)
Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. ISSCC (2008)
Ping-Ying Wang, Hsiu-Ming Chang
A charge pump-based direct frequency modulator. ISCAS (2008)
Ping-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. ISSCC (2007)
Ping-Ying Wang, C.-H. Chou, Hsueh-Wu Kao
Chaos in delay locked loop. ISCAS (2006)
Ping-Ying Wang, Hsiang Ji Hsieh, Yung-Yu Lin, Meng-Ta Yang, Hsueh-Wu Kao
A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives. ISCAS (5) (2005)