Hsiang-Hui Chang

Publication Activity (10 Years)

Years Active: 2002-2013
Publications (10 Years): 0

Top Topics

Top Venues

IEEE J. Solid State Circuits

Publications

Tzung-Han Wu, Hsiang-Hui Chang, Shin-Fu Chen, Chinq-Shiun Chiu, Li-Shin Lai, Chi-Hsueh Wang, Song-Yu Yang, Ta-Hsin Lin, Jhy-Rong Chen, Hung-Chieh Tsai, Chi-Yao Yu, Sheng-Yuan Su, Tai-Yuan Yu, Chieh-Chuan Chin, Guang-Kaai Dehng, Augusto Marques, Caiyi Wang, George Chien
A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM. IEEE J. Solid State Circuits 48 (5) (2013)
Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. IEEE J. Solid State Circuits 46 (12) (2011)
Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. A-SSCC (2011)
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. IEEE J. Solid State Circuits 44 (8) (2009)
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. CICC (2008)
Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan
A fractional spur reduction technique for RF TDC-based all digital PLLs. ESSCIRC (2008)
Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. ISSCC (2008)
Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu
A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE J. Solid State Circuits 41 (5) (2006)
Hsiang-Hui Chang, Shen-Iuan Liu
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop. IEEE J. Solid State Circuits 40 (3) (2005)
Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2004)
Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu
A shifted-averaging VCO with precise multiphase outputs and low jitter operation. ESSCIRC (2003)
Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu
A fast locking and low jitter delay-locked loop using DHDL. IEEE J. Solid State Circuits 38 (2) (2003)
Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu
A spread-spectrum clock generator with triangular modulation. IEEE J. Solid State Circuits 38 (4) (2003)
Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay. CICC (2002)
Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu
A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits 37 (8) (2002)