Lan-Chou Cho

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 6

Top Topics

Fully Integrated

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS (2024)
Kai Xu, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
Self-Suppression and Pulling Mitigation. IEEE J. Solid State Circuits 54 (7) (2019)
Feng-Wei Kuo, Zhirui Zong, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. ESSCIRC (2019)
Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Feng-Wei Kuo, Sandro Binsfeld Ferreira, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Iman Madadi, Massoud Tohidian, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. IEEE J. Solid State Circuits 52 (4) (2017)
Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. IEEE J. Solid State Circuits 51 (7) (2016)
YuLi Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai, Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, Jing-Hong Conan Zhan
frequency synthesizer in 40nm CMOS with 0.19psrms jitter and. ISSCC (2014)
Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. A-SSCC (2011)
Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. IEEE J. Solid State Circuits 44 (3) (2009)
Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology. ISSCC (2008)
Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS. IEEE Trans. Circuits Syst. II Express Briefs (5) (2008)
Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS. ISSCC (2007)
Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology. IEEE J. Solid State Circuits 42 (6) (2007)