Chua-Chin Wang

ORCID

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 86

Top Venues

Publications

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo
A single-chip PFM-controlled LED driver with 0.5% illuminance variation. Microelectron. J. 147 (2024)
Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS (2024)
Oliver Lexter July A. Jose, Yun-Che Chang, Venkata Naveen Kolakaluri, Celso B. Co, Mitch Ming-Chi Chou, Chua-Chin Wang
A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process. ISCAS (2024)
Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic. Integr. 98 (2024)
Cheng-Yao Lo, Lean Karlo Santos Tolentino, Jhih-Ying Ke, Jeffrey S. Walling, Yang Yi, Chua-Chin Wang
A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process. AICAS (2024)
Soumika Majumder, Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. ISCAS (2024)
Chua-Chin Wang, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador
A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. Circuits Syst. Signal Process. 43 (6) (2024)
Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. 32 (5) (2024)
Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang
GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. AICAS (2024)
Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder. MWSCAS (2023)
Ralph Gerard B. Sangalang, Shih-Heng Luo, Chua-Chin Wang
A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process. ICICDT (2023)
Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Integr. 90 (2023)
Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. ASICON (2023)
Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle. ISCAS (2023)
Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose
A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process. IET Circuits Devices Syst. 17 (2) (2023)
Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang
2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. APCCAS (2023)
Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang
A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. APCCAS (2023)
Oliver Lexter July A. Jose, Jui-Min Kuo, Venkata Naveen Kolakaluri, Chua-Chin Wang
SiC MOSFET High Side Gate Driver Design Using HV CMOS Process. MWSCAS (2023)
Ralph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang
A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process. APCCAS (2023)
Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst. Signal Process. 42 (4) (2023)
Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS (2022)
Shiva Reddy, Ralph Gerard B. Sangalang, Chua-Chin Wang
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process. ICICDT (2022)
Li Lin, Lean Karlo S. Tolentino, Chua-Chin Wang
A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture. ISCAS (2022)
Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Chia-Hung Yeh, Chu-Han Lin, Li-Wei Kang, Chih-Hsiang Huang, Min-Hui Lin, Chuan-Yu Chang, Chua-Chin Wang
Lightweight Deep Neural Network for Joint Learning of Underwater Object Detection and Color Conversion. IEEE Trans. Neural Networks Learn. Syst. 33 (11) (2022)
Jyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang
A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. APCCAS (2022)
Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang
A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic. ICICDT (2022)
Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang
A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. APCCAS (2022)
Tzung-Je Lee, Bo-Hao Liao, Chua-Chin Wang
Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique. ICICDT (2022)
Pang-Yen Lou, Ying-Xuan Chen, Chua-Chin Wang
On-chip CMOS Corner Detector Design for Panel Drivers. ISOCC (2021)
Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang
A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop. ISCAS (2021)
Pang-Yen Lou, Yung-Yuan Ho, Chua-Chin Wang
Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer. ISOCC (2021)
Tzung-Je Lee, Wen-Shou Yang, Chua-Chin Wang
A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology. APCCAS (2021)
Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng
A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit. IEEE Trans. Circuits Syst. II Express Briefs 68 (12) (2021)
Chua-Chin Wang, Chia-Yi Huang, Chia-Hung Yeh
SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction. ISCAS (2021)
Yu-Cheng Chou, Hsin-Hung Chen, Chau-Chang Wang, Hui-Min Chou, Chua-Chin Wang
An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset. AICAS (2021)
Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee
2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. Circuits Syst. Signal Process. 40 (6) (2021)
Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, I-Yu Huang, Yu-Cheng Lin, Tzung-Je Lee, Guan-Ru Chen
High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors. Circuits Syst. Signal Process. 40 (9) (2021)
Chua-Chin Wang, Chien-Ping Kuo
200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Chua-Chin Wang, Pang-Yen Lou, Zong-You Hou, Hsiu-Chun Tsai
0.7 % error rate 3A bidirectional current sensor using high voltage CMOS process. Microelectron. J. 114 (2021)
Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. Microelectron. J. 118 (2021)
Chua-Chin Wang, Lean Karlo S. Tolentino, Chia-Yi Huang, Chia-Hung Yeh
A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM. IEEE Trans. Very Large Scale Integr. Syst. 29 (12) (2021)
Chua-Chin Wang
Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Chua-Chin Wang, Chien-Ping Kuo
67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process. ISCAS (2021)
Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino, Chua-Chin Wang
A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. APCCAS (2021)
Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang
2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations. J. Circuits Syst. Comput. 29 (6) (2020)
Tzung-Je Lee, Ssu-Wei Huang, Chua-Chin Wang
A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. IEEE Trans. Circuits Syst. (11) (2020)
Chua-Chin Wang, Chia-Yi Huang, Chu-Han Lin, Chia-Hung Yeh, Guan-Xian Liu, Yu-Cheng Chou
3D-Modeling Dataset Augmentation for Underwater AUV Real-time Manipulations. APCCAS (2020)
Chua-Chin Wang, Zong-You Hou, Deng-Shian Wang, Chia-Lung Hsieh
A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry. J. Circuits Syst. Comput. 29 (6) (2020)
Chua-Chin Wang, Shao-Wei Lu
. APCCAS (2020)
Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, Ponnan Suresh
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Chua-Chin Wang, Nanang Sulistiyanto, Hsiang-Yu Shih, Yu-Cheng Lin, Wei Wang
Power-effective ROM-less DDFS Design Approach with High SFDR Performance. J. Signal Process. Syst. 92 (2) (2020)
Chun-Ting Chen, Tsung-Yi Tsai, Yi-Jen Chiu, Chua-Chin Wang
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems. ASICON (2019)
Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Tsung-Yi Tsai, Ting-Sheng Wang, Yi-Jen Chiu, Chua-Chin Wang
A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs. ICICDT (2019)
Tzung-Je Lee, Chia-Hsin Hsu, Chua-Chin Wang
High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM. ISCAS (2019)
Nanang Sulistiyanto, Chua-Chin Wang, Robert Rieger
A Low Frequency OTA Design with Temperature-Insensitive Variable Transconductance Using 180-nm CMOS Technology. ICICDT (2019)
Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. IEEE Trans. Circuits Syst. II Express Briefs (1) (2019)
Pang-Yen Lou, Chien-Hua Chu, Chua-Chin Wang
. ICCE (2019)
Chua-Chin Wang, I-Ting Tseng
Ultra Low Power Single-ended 6T SRAM Using 40 nm CMOS Technology. ICICDT (2019)
Chua-Chin Wang, Guan-Xian Liu
A 1.5A 88.6% Li-ion Battery Charger Design using Pulse Swallow Technique in Light Load. ISCAS (2019)
Chua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee
500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations. Circuits Syst. Signal Process. 38 (2) (2019)
Chua-Chin Wang, Zong-You Hou, Chih-Lin Chen, Doron Shmilovitz
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits. Circuits Syst. Signal Process. 37 (4) (2018)
Chua-Chin Wang, Zong-You Hou, Jhih-Cheng You
A High-Precision CMOS Temperature Sensor with Thermistor Linear Calibration in the (-5 °C, 120 °C) Temperature Range. Sensors 18 (7) (2018)
Hao-Chun Huang, Deng-Shian Wang, Chua-Chin Wang
A frequency-shift readout system with offset cancellation OPA for portable devices of marijuana detection. ICCE (2018)
Chua-Chin Wang, Zong-You Hou, Ssu-Wei Huang
40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate. APCCAS (2018)
Zong-You Hou, Zong-Ying Ho, Jhih-Cheng You, Chua-Chin Wang
A primary-side output current estimator with process compensator for flyback LED drivers. ISCAS (2017)
Je-Wei Lan, Chia-Hsu Hsieh, I-Yu Huang, Yu-Cheng Lin, Tsung-Yi Tsai, Chua-Chin Wang
Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine. Sensors 17 (12) (2017)
Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang
A pipeline ROM-less DDFS using equal-division interpolation. ISOCC (2017)
Wen-Hui Huang, I-Yu Huang, Yu-Shan Tseng, Chia-Hsu Hsieh, Chua-Chin Wang
A 19.38 dBm OIP3 gm-boosted up-conversion CMOS mixer for 5-6 GHz application. Microelectron. J. 60 (2017)
Chua-Chin Wang, Zong-You Hou, Kai-Wei Ruan
2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation. IEEE Trans. Circuits Syst. II Express Briefs (7) (2017)
Deng-Shian Wang, Yu-Hsun Su, Chua-Chin Wang
A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM. Microelectron. J. 70 (2017)
Zong-You Hou, Hsiu-Chun Tsai, Chua-Chin Wang
High-voltage bidirectional current sensor. ASICON (2017)
Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Wei Wang, Yuan-Yuan Xu, Chua-Chin Wang
Dynamic power estimation for ROM-less DDFS designs using switching activity analysis. ISOCC (2017)
Zong-You Hou, Pang-Yen Lou, Chua-Chin Wang
State of charge, state of health, and state of function monitoring for EV BMS. ICCE (2017)
Tsung-Yi Tsai, Yu-Lin Teng, Chua-Chin Wang
A nano-scale 2×VDD I/O buffer with encoded PV compensation technique. ISCAS (2016)
Deng-Shian Wang, Yun-Shen Liu, Chua-Chin Wang
A novel frequency-shift readout system for CEA concentration detection application. ISOCC (2016)
Chua-Chin Wang, Zong-You Hou, Teng-Wei Huang
A flyback driver with adaptive switching frequency control for smart lighting1. ICCE (2016)
Yu-Ting Tu, Deng-Shian Wang, Chua-Chin Wang
An accurate phase shift detector using bulk voltage boosting technique for sensing applications. ISCAS (2016)
Chua-Chin Wang, Chia-Lung Hsieh
Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process. ISOCC (2016)
Chua-Chin Wang, Zong-You Hou, Wen-Je Lu, Sheng-Syong Wang
High-voltage on-chip current sensor design and analysis for battery modules. IET Circuits Devices Syst. 10 (6) (2016)
Zong-You Hou, Teng-Wei Huang, Chua-Chin Wang
On-chip accurate primary-side output current estimator for flyback LED driver control. ICICDT (2016)
Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang
A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above. ICICDT (2016)
Chua-Chin Wang, Deng-Shian Wang, Chiang-Hsiang Liao, Sih-Yu Chen
A Leakage Compensation Design for Low Supply Voltage SRAM. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin
A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology. ICICDT (2015)
Chua-Chin Wang, Chih-Lin Chen, Zong-You Hou, Yi Hu, Jam-Wem Lee, Wan-Yen Lin, Yi-Feng Chang, Chia-Wei Hsu, Ming-Hsiang Song
A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Chua-Chin Wang, Deng-Shian Wang, Tzu-Chiao Sung, Yi-Jie Hsieh, Tzung-Je Lee
A ±3.07% frequency variation clock generator implemented using HV CMOS process. Microelectron. J. 46 (4) (2015)
Chua-Chin Wang, Tsung-Yi Tsai, Wen-Je Lu, Chih-Lin Chen, Yi-Lun Wu
A 30 V rail-to-rail operational amplifier. Microelectron. J. 46 (10) (2015)
Chua-Chin Wang, Wen-Je Lu, Kai-Wei Juan, Wei Lin, Hsin-Yuan Tseng, Chun-Ying Juan
Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology. Microelectron. J. 46 (1) (2015)
Chua-Chin Wang, Min-Yu Tseng
10 Mbps high-voltage digital transciever on single die for 50 V voltage swing. ASICON (2015)
Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang
A wide range and high conversion gain power detector for frequency shift sensing applications. MWSCAS (2015)
Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang
A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang
A high-voltage Transceiver for electrical vehicle Battery Management Systems. ICCE (2015)
Chua-Chin Wang, Wen-Je Lu, Tzu-Chao Wu
Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring. Microelectron. J. 46 (9) (2015)
Chua-Chin Wang, Wen-Je Lu, Tsung-Yi Tsai
Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips. IEEE Trans. Circuits Syst. II Express Briefs (3) (2015)
Chua-Chin Wang, Wen-Je Lu, Tzu-Chao Wu, Chun-Ying Juan
A CMOS wide-range temperature sensor with process compensation and second-order calibration for Battery Management Systems. ISCAS (2014)
Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang
A 20 GHz power detector with 176 mV/dB conversion gain. APCCAS (2014)
Chua-Chin Wang, Wen-Je Lu, Sheng-Syong Wang
An on-chip high-voltage current sensor for battery module monitoring. ICICDT (2014)

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Publication Activity (10 Years)

Top Topics

Top Venues

Chua-Chin Wang