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GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process.
Jhih-Ying Ke
Lean Karlo Santos Tolentino
Cheng-Yao Lo
Tzung-Je Lee
Chua-Chin Wang
Published in:
AICAS (2024)
Keyphrases
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genetic algorithm
design process
genetic algorithm ga
engineering design
simulated annealing
input output
optimization method
neural network
database systems
evolutionary algorithm
multi objective
particle swarm optimization
optimization algorithm
design tools