Login / Signup

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process.

Jhih-Ying KeLean Karlo Santos TolentinoCheng-Yao LoTzung-Je LeeChua-Chin Wang
Published in: AICAS (2024)
Keyphrases