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A ±3.07% frequency variation clock generator implemented using HV CMOS process.
Chua-Chin Wang
Deng-Shian Wang
Tzu-Chiao Sung
Yi-Jie Hsieh
Tzung-Je Lee
Published in:
Microelectron. J. (2015)
Keyphrases
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high speed
genetic algorithm
neural network
data sets
similarity measure
digital libraries
low frequency
duty cycle