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A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment.

Tzung-Je LeeWen-Jian SuLean Karlo S. TolentinoChua-Chin Wang
Published in: APCCAS (2021)
Keyphrases
  • duty cycle
  • clock frequency
  • cmos technology
  • buffer size
  • power consumption
  • real time
  • high speed
  • parallel computing
  • high end