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A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry.
Chua-Chin Wang
Zong-You Hou
Deng-Shian Wang
Chia-Lung Hsieh
Published in:
J. Circuits Syst. Comput. (2020)
Keyphrases
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circuit design
cmos technology
power consumption
high speed
design process
neural network
knowledge based systems
engineering design
single chip
power reduction
nm technology
case study
low cost
low power
chip design