A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology.
Jyoshnavi AkiriLean Karlo S. TolentinoLung-Jieh YangBalasubramanian EsakkiSivaperumal SampathChua-Chin WangPublished in: APCCAS (2022)
Keyphrases
- cmos technology
- shift register
- low power
- high speed
- random number generator
- spl times
- low voltage
- hardware implementation
- power consumption
- parallel processing
- random number
- image sensor
- flip flops
- mixed signal
- power dissipation
- silicon on insulator
- pattern recognition
- frame rate
- digital signal processing
- multi channel
- low cost
- real time