A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process.
Ralph Gerard B. SangalangShiva ReddyLean Karlo S. TolentinoYou-Wei ShenOliver Lexter July A. JoseChua-Chin WangPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2023)
Keyphrases
- nm technology
- power consumption
- energy efficiency
- cmos technology
- random access memory
- energy saving
- low power
- clock gating
- low voltage
- knowledge base
- energy efficient
- energy consumption
- power reduction
- power management
- power saving
- high speed
- low cost
- power dissipation
- energy minimization
- minimum energy
- data transmission
- data center
- low energy
- design considerations
- flip flops
- leakage current
- x ray