Oliver Lexter July A. Jose

Publication Activity (10 Years)

Years Active: 2021-2024
Publications (10 Years): 16

Top Topics

Random Access Memory

Cmos Technology

Top Venues

Circuits Syst. Signal Process.

Publications

Oliver Lexter July A. Jose, Yun-Che Chang, Venkata Naveen Kolakaluri, Celso B. Co, Mitch Ming-Chi Chou, Chua-Chin Wang
A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process. ISCAS (2024)
Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic. Integr. 98 (2024)
Soumika Majumder, Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. ISCAS (2024)
Chua-Chin Wang, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador
A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. Circuits Syst. Signal Process. 43 (6) (2024)
Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. 32 (5) (2024)
Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder. MWSCAS (2023)
Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Integr. 90 (2023)
Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle. ISCAS (2023)
Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose
A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process. IET Circuits Devices Syst. 17 (2) (2023)
Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang
2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. APCCAS (2023)
Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Oliver Lexter July A. Jose, Jui-Min Kuo, Venkata Naveen Kolakaluri, Chua-Chin Wang
SiC MOSFET High Side Gate Driver Design Using HV CMOS Process. MWSCAS (2023)
Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst. Signal Process. 42 (4) (2023)
Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang
A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic. ICICDT (2022)
Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang
A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. APCCAS (2022)
Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. Microelectron. J. 118 (2021)