A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.
Chua-Chin WangLean Karlo S. TolentinoShao-Wei LuOliver Lexter July A. JoseRalph Gerard B. SangalangTzung-Je LeePang-Yen LouWei-Chih ChangPublished in: Integr. (2023)