Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process.
Chua-Chin WangKuan-Yu ChaoSivaperumal SampathPonnan SureshPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2020)
Keyphrases
- low power
- mixed signal
- cmos technology
- low cost
- power consumption
- analog to digital converter
- single chip
- high speed
- nm technology
- low voltage
- digital signal processing
- vlsi architecture
- low power consumption
- logic circuits
- power reduction
- power dissipation
- vlsi circuits
- cmos image sensor
- gate array
- ultra low power
- high power
- control method
- wireless transmission
- multi channel
- design process
- digital circuits
- image sensor
- data conversion