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A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM.
Deng-Shian Wang
Yu-Hsun Su
Chua-Chin Wang
Published in:
Microelectron. J. (2017)
Keyphrases
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cmos technology
power consumption
low power
low voltage
high speed
nm technology
circuit design
analog vlsi
silicon on insulator
parallel processing
power dissipation
power reduction
leakage current
delay insensitive
low cost
vlsi circuits
neural network
real time
mixed signal