A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology.

Chua-Chin Wang Tsung-Yi Tsai Wei Lin

Published in: ICICDT (2015)

Keyphrases

cmos technology
low power
high speed
low cost
power consumption
spl times
low voltage
parallel processing
mixed signal
object detection
digital signal processing
power dissipation
silicon on insulator
real time
image sensor
digital images
pattern recognition
machine vision
clock frequency