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A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop.
Uday Kiran Naidu Ekkurthi
Venkatesh Dasari
Jyoshnavi Akiri
Chua-Chin Wang
Published in:
ISCAS (2021)
Keyphrases
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flip flops
shift register
high speed
power consumption
power dissipation
random number generator
multiple input
low power
cmos technology
hardware implementation
edge detection
master slave
random number
signal processing
neural network
object oriented
digital images
pattern recognition
image processing