A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer.
Tzung-Je LeeTsung-Yi TsaiWei LinU-Fat ChioChua-Chin WangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
- low voltage
- cmos technology
- leakage current
- high speed
- circuit design
- analog vlsi
- power consumption
- low power
- power supply
- silicon on insulator
- clock gating
- nm technology
- buffer size
- power dissipation
- power system
- low cost
- delay insensitive
- vlsi circuits
- parallel processing
- dynamic environments
- dynamic response
- real time
- energy dissipation
- chip design