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2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation.

Chua-Chin WangZong-You HouKai-Wei Ruan
Published in: IEEE Trans. Circuits Syst. II Express Briefs (2017)
Keyphrases
  • buffer size
  • high speed
  • cmos technology
  • power consumption
  • power supply
  • low cost
  • low power
  • data sets
  • silicon on insulator
  • code length
  • neural network
  • control system
  • transmission rate
  • nm technology