A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit.
Chua-Chin WangRalph Gerard B. SangalangI-Ting TsengPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2021)
Keyphrases
- low power
- cmos technology
- power reduction
- power consumption
- high speed
- logic circuits
- nm technology
- power dissipation
- low cost
- single chip
- gate array
- low voltage
- low power consumption
- vlsi architecture
- mixed signal
- vlsi circuits
- power saving
- digital signal processing
- high power
- delay insensitive
- wireless transmission
- ultra low power
- real time
- circuit design
- image sensor
- energy saving
- low complexity
- embedded dram
- signal processing