Shen-Fu Hsiao

Publication Activity (10 Years)

Years Active: 1991-2022
Publications (10 Years): 27

Top Topics

Piecewise Polynomial

Top Venues

Publications

Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS (2022)
Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Shen-Fu Hsiao, Hung-Ching Li, Yu-Che Yen, Po-Chang Li
Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination. ISCAS (2022)
Shen-Fu Hsiao, Yu-Che Yen
Quantization of Deep Neural Network Models Considering Per-Layer Computation Complexity for Efficient Execution in Multi-Precision Accelerators. ICCE-TW (2021)
Shen-Fu Hsiao, Bo-Ching Tsai
Efficient Computation of Depthwise Separable Convolution in MoblieNet Deep Neural Network Models. ICCE-TW (2021)
Shen-Fu Hsiao, Jian-Ming Chen, Yu-Hong Chen, Hung-Ching Li, Yi Hsu
Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. ISCAS (2021)
Shen-Fu Hsiao, Jyun-Liang Chen, Yi Hsu, Xiang-Ting Huang
Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage. ICCE-TW (2021)
Shen-Fu Hsiao, Yu-Chang Chen, Yu-Che Yen
Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning. ISCAS (2021)
Shen-Fu Hsiao, Chia-Yang Wong, Yu-Chang Chen
Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation. ISCAS (2020)
Shen-Fu Hsiao, Yu-Hong Chen
Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication. VLSI-DAT (2020)
Shen-Fu Hsiao, Hsuan-Jui Chang
Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations. ISCAS (2020)
Shen-Fu Hsiao, Kun-Chih Chen, Chih-Chien Lin, Hsuan-Jui Chang, Bo-Ching Tsai
Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (3) (2020)
Shen-Fu Hsiao, Jing-Fu Zhan, Chih-Chien Lin
Low-Complexity Deep Neural Networks for Image Object Classification and Detection. APCCAS (2019)
Shen-Fu Hsiao, Pei-Hsuan Wu, Jien-Min Chen, Kun-Chih Chen
Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse. ISCAS (2019)
Shen-Fu Hsiao, Kuey-Chin Huang, Yu-Hong Chen
Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks. APCCAS (2019)
Shen-Fu Hsiao, Yu-Chang Chen, Hsiang-Hao Liang
Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks. DSD (2018)
Shen-Fu Hsiao, Kun-Chih Chen, Yi-Hau Chen
Optimization of Lookup Table Size in Table-Bound Design of Function Computation. ISCAS (2018)
Shen-Fu Hsiao, Pei-Hsuen Wu
Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators. GCCE (2018)
Shen-Fu Hsiao, Chih-Hsuan Chang
Hardware design of disparity computation for stereo vision using guided image filtering. VLSI-DAT (2018)
Shen-Fu Hsiao, Chen-Yen Tsai
Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels. DSD (2018)
Shen-Fu Hsiao, Tz-Heng Tz-Heng You
Hardware efficient implementation of histograms of oriented gradients for pedestrian detection. GCCE (2017)
Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang
Hierarchical Multipartite Function Evaluation. IEEE Trans. Computers 66 (1) (2017)
Shen-Fu Hsiao, Jun-Mao Chan, Ching-Hui Wang
Hardware design of histograms of oriented gradients based on local binary pattern and binarization. APCCAS (2016)
Shen-Fu Hsiao, Kuei-Chun Huang
Low-power dual-precision table-based function evaluation supporting dynamic precision changes. APCCAS (2016)
Shen-Fu Hsiao, Shang-Yu Li, Kai-Hsiang Tsao
Low-power and high-performance design of OpenGL ES 2.0 graphics processing unit for mobile applications. DSP (2015)
Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT (2015)
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs (5) (2015)
Shen-Fu Hsiao, Guan-Fu Yeh, Je-Chi Chen
Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning. DSD (2014)
Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu
Compression of Lookup Table for Piecewise Polynomial Function Evaluation. DSD (2014)
Shen-Fu Hsiao, Pu-Cheng Wu
Design of low-leakage multi-port SRAM for register file in graphics processing unit. ISCAS (2014)
Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu
VLSI implementations of stereo matching using Dynamic Programming. VLSI-DAT (2014)
Shen-Fu Hsiao, Jun-Ming Huang, Po-Sheng Wu
VLSI implementation of belief-propagation-based stereo matching with linear-model message update. APCCAS (2014)
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen
Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. VLSI-DAT (2013)
Shen-Fu Hsiao, Jun-Hong Zhang Jian, Ming-Chih Chen
Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation. IEEE Trans. Circuits Syst. II Express Briefs (5) (2013)
Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. IEEE Trans. Very Large Scale Integr. Syst. 21 (5) (2013)
Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. IEEE Trans. Circuits Syst. II Express Briefs (5) (2012)
Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen
Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. APCCAS (2012)
Shen-Fu Hsiao, Jin-Wen Cheng, Wen-Ling Wang, Guan-Fu Yeh
Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling. ISCAS (2012)
Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee
Low-cost designs of rectangular to polar coordinate converters for digital communication. APCCAS (2012)
Shen-Fu Hsiao, Cheng-Han Lee, Yen-Chun Cheng, Andrew Lee
Designs of angle-rotation in digital frequency synthesizer/mixer using multi-stage architectures. ACSCC (2011)
Hou-Jen Ko, Shen-Fu Hsiao
Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding. IEEE Trans. Circuits Syst. II Express Briefs (5) (2011)
Hou-Jen Ko, Shen-Fu Hsiao, Wen-Liang Huang
A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation. ISCAS (2010)
Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen
Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method. APCCAS (2010)
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. IEEE Trans. Circuits Syst. II Express Briefs (1) (2010)
Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC (2009)
Ming-Chih Chen, Shen-Fu Hsiao
Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Shen-Fu Hsiao, Hsin-Mau Lee, Yen-Chun Cheng, Ming-Yu Tsai
Efficient designs of flaoting-point CORDIC rotation and vectoring operations. APCCAS (2008)
Shen-Fu Hsiao, Yuan-Nan Chang, Tze-Ching Tien, Kun-Chih Chen
Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation. APCCAS (2008)
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ISCAS (2008)
Shen-Fu Hsiao, Ping-Chung Wei, Ching-Pin Lin
An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. ISCAS (2008)
Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. MTDT (2006)
Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chong Cheng, Ming-Yu Tsai
An Automatic Cache Generator Based on Content-Addressable Memory. APCCAS (2006)
Shen-Fu Hsiao, Ming-Chih Chen, Chia-Shin Tu
Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2006)
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. APCCAS (2006)
Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. IEICE Trans. Inf. Syst. (7) (2005)
Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ISCAS (3) (2005)
Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, Cheng-Han Lee
Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2005)
Tso-Bing Juang, Shen-Fu Hsiao
Low-error carry-free fixed-width multipliers with low-cost compensation circuits. IEEE Trans. Circuits Syst. II Express Briefs (6) (2005)
Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang
A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations. IEEE Signal Process. Lett. 11 (2) (2004)
Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai
Para-CORDIC: parallel CORDIC rotation algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2004)
Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang
Design and implementation of a video-oriented network-interface-card system. ASP-DAC (2003)
Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao
Partition methodology for the final adder in a tree-structure parallel multiplier generator. APCCAS (1) (2002)
Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen
High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic. VLSI Design 2002 (1) (2002)
Shen-Fu Hsiao, Wei-Ren Shiue
A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array. IEEE Trans. Circuits Syst. Video Technol. 11 (11) (2001)
Shen-Fu Hsiao, Jian-Ming Tseng
Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec. J. VLSI Signal Process. 28 (3) (2001)
Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen
High-performance multiplexer-based logic synthesis using pass-transistor logic. ISCAS (2000)
Shen-Fu Hsiao, Wei-Ren Shiue
Low-cost unified architectures for the computation of discrete trigonometric transforms. ICASSP (2000)
Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme
Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD. J. VLSI Signal Process. 25 (2) (2000)
Shen-Fu Hsiao, Yor-Chin Tai, Kai-Hsiang Chang
VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking. IEEE Trans. Consumer Electron. 46 (3) (2000)
Shen-Fu Hsiao, Wei-Ren Shiue, Jian-Ming Tseng
A cost-efficient and fully-pipelinable architecture for DCT/IDCT. IEEE Trans. Consumer Electron. 45 (3) (1999)
Shen-Fu Hsiao, Wei-Ren Shiue
New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array. ICASSP (1999)
Chua-Chin Wang, Sheng-Hua Chen, Shen-Fu Hsiao, Chuan-Lin Wu
Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology. ICECS (1999)
Shen-Fu Hsiao
A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations. ISCAS (1) (1999)
Shen-Fu Hsiao, Wei-Ren Shiue
A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation. ICASSP (1999)
Shen-Fu Hsiao, Jen-Yin Chen
Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure. J. VLSI Signal Process. 20 (3) (1998)
Shen-Fu Hsiao, Chung-Yi Yen
New unified VLSI architectures for computing DFT and other transforms. ICASSP (1997)
Shen-Fu Hsiao, Jean-Marc Delosme
Parallel singular value decomposition of complex matrices using multidimensional CORDIC algorithms. IEEE Trans. Signal Process. 44 (3) (1996)
Shen-Fu Hsiao
Adaptive Jacobi method for parallel singular value decompositions. ICASSP (1995)
Shen-Fu Hsiao, Jean-Marc Delosme
Householder CORDIC Algorithms. IEEE Trans. Computers 44 (8) (1995)
Shen-Fu Hsiao, Jean-Marc Delosme
Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms. ASAP (1994)
Shen-Fu Hsiao, Jean-Marc Delosme
The CORDIC Householder algorithm. IEEE Symposium on Computer Arithmetic (1991)