Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment.
Shen-Fu HsiaoMing-Yu TsaiChia-Sheng WenPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2010)
Keyphrases
- chip design
- power dissipation
- circuit design
- high speed
- power consumption
- manufacturing cell
- logic synthesis
- low cost
- low power
- inter cell
- low power consumption
- cell formation
- microscopy images
- digital circuits
- cell lines
- real time
- ultra low power
- delay insensitive
- layout design
- digital signal processing
- simulation environment
- hybrid learning
- neural network