Chia-Sheng Wen

Publication Activity (10 Years)

Years Active: 2005-2017
Publications (10 Years): 1

Top Topics

Reduction Method

Piecewise Polynomial

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Computers

Publications

Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang
Hierarchical Multipartite Function Evaluation. IEEE Trans. Computers 66 (1) (2017)
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs (5) (2015)
Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu
Compression of Lookup Table for Piecewise Polynomial Function Evaluation. DSD (2014)
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen
Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. VLSI-DAT (2013)
Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. IEEE Trans. Very Large Scale Integr. Syst. 21 (5) (2013)
Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. IEEE Trans. Circuits Syst. II Express Briefs (5) (2012)
Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen
Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. APCCAS (2012)
Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee
Low-cost designs of rectangular to polar coordinate converters for digital communication. APCCAS (2012)
Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen
Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method. APCCAS (2010)
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. IEEE Trans. Circuits Syst. II Express Briefs (1) (2010)
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ISCAS (2008)
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. APCCAS (2006)
Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ISCAS (3) (2005)