Hou-Jen Ko

Publication Activity (10 Years)

Years Active: 2007-2018
Publications (10 Years): 1

Top Topics

Evaluation Criteria

Hardware Design

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Hou-Jen Ko, Zhiyuan Li, Samuel P. Midkiff
Optimizing data layout and system configuration on FPGA-based heterogeneous platforms. ICCAD (2018)
Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. IEEE Trans. Very Large Scale Integr. Syst. 21 (5) (2013)
Hongtao Yu, Hou-Jen Ko, Zhiyuan Li
General data structure expansion for multi-threading. PLDI (2013)
Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. IEEE Trans. Circuits Syst. II Express Briefs (5) (2012)
Hou-Jen Ko, Shen-Fu Hsiao
Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding. IEEE Trans. Circuits Syst. II Express Briefs (5) (2011)
Hou-Jen Ko, Shen-Fu Hsiao, Wen-Liang Huang
A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation. ISCAS (2010)
Hou-Jen Ko, Chun-Jen Tsai
A Double-Issue Java Processor Design for Embedded Applications. ISCAS (2007)