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Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology.
Chua-Chin Wang
Sheng-Hua Chen
Shen-Fu Hsiao
Chuan-Lin Wu
Published in:
ICECS (1999)
Keyphrases
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cmos technology
low power
spl times
power consumption
case study
design process
single chip
power dissipation
low voltage
low cost
design methodology
efficient implementation