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A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array.
Shen-Fu Hsiao
Wei-Ren Shiue
Published in:
IEEE Trans. Circuits Syst. Video Technol. (2001)
Keyphrases
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linear array
computational complexity
hardware implementation
optimal solution
hardware architecture
pipelined architecture
real time
np hard
worst case
computer systems
parallel implementation
low cost
computing systems