Tso-Bing Juang

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 6

Top Topics

Computationally Intensive

Convolutional Neural Network

Top Venues

Publications

Tso-Bing Juang, Chun-Chi Fan, Guan-Zhong Lin
Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS). ISOCC (2023)
Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin
Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems. ISOCC (2019)
Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin
Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems. ISOCC (2018)
Tso-Bing Juang, Ying-Ren Lee
Low-area implementations of concurrent error detection logarithmic processors. ISOCC (2017)
Tso-Bing Juang, Ying-Ren Lee, Chin-Chieh Chiu
Low-cost concurrent error detection schemes for logarithmic converters. ISOCC (2016)
Tso-Bing Juang, Ying-Ren Lee
Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications. ISVLSI (2016)
Tso-Bing Juang, Yu-Ming Chiu
Fast binary to BCD converters for decimal communications using new recoding circuits. ISIC (2014)
Chao-Tsung Kuo, Tso-Bing Juang
A lower error antilogarithmic converter using novel four-region piecewise-linear approximation. APCCAS (2012)
Tso-Bing Juang, Jian-Hao Huang
±1) multipliers based on modified booth encoding. APCCAS (2012)
Tso-Bing Juang, Hsin-Hao Peng, Han-Lung Kuo
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders. ISOCC (2012)
Tso-Bing Juang, Chao-Tsung Kuo, Go-Long Wu, Jian-Hao Huang
± 1 Multipliers. J. Circuits Syst. Comput. 21 (4) (2012)
Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo
Area-efficient 3-input decimal adders using simplified carry and sum vectors. VLSI-SoC (2011)
Tso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan
Area-efficient parallel-prefix Ling adders. APCCAS (2010)
Tso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai
+ 1 Adder Design With Simple Correction Schemes. IEEE Trans. Circuits Syst. II Express Briefs (3) (2010)
Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu
+ 1 Adder Using Circular Carry Selection" [Sep 08 897-901]. IEEE Trans. Circuits Syst. II Express Briefs (3) (2009)
Pramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna
50 Years of CORDIC: Algorithms, Architectures, and Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Tso-Bing Juang, Sheng-Hung Chen, Huang-Jia Cheng
A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs (12) (2009)
Tso-Bing Juang
Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations. IEEE Trans. Circuits Syst. II Express Briefs (11) (2008)
Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li
A novel VLSI iterative divider architecture for fast quotient generation. ISCAS (2008)
Tso-Bing Juang
Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations. APCCAS (2006)
Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. IEICE Trans. Inf. Syst. (7) (2005)
Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, Cheng-Han Lee
Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2005)
Tso-Bing Juang, Shen-Fu Hsiao
Low-error carry-free fixed-width multipliers with low-cost compensation circuits. IEEE Trans. Circuits Syst. II Express Briefs (6) (2005)
Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang
A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations. IEEE Signal Process. Lett. 11 (2) (2004)
Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai
Para-CORDIC: parallel CORDIC rotation algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2004)
Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao
Partition methodology for the final adder in a tree-structure parallel multiplier generator. APCCAS (1) (2002)