A novel VLSI iterative divider architecture for fast quotient generation.
Tso-Bing JuangSheng-Hung ChenShin-Mao LiPublished in: ISCAS (2008)
Keyphrases
- vlsi architecture
- vlsi implementation
- real time
- data driven
- layered architecture
- vlsi design
- management system
- data sets
- multi agent
- high speed
- pattern recognition
- signal processing
- case study
- data flow
- design methodology
- reference model
- generation process
- design considerations
- iterative methods
- master slave
- website
- social networks
- information retrieval