Javier Valls

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 19

Top Topics

Decoding Algorithm

Low Density Parity Check

Fpga Implementation

Tips And Tricks

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Commun. Lett.

Publications

Gerardo José Ginovart-Panisello, Ignasi Iriondo, Tesa Panisello Monjo, Silvia Riva, Rodrigo Garcia, Javier Valls, Rosa Maria Alsina Pages
Acoustic detection of the effects of prolonged fasting on newly hatched broiler chickens. Comput. Electron. Agric. 219 (2024)
Julien du Crest, Francisco Garcia-Herrero, Mehdi Mhalla, Valentin Savin, Javier Valls
Layered Decoding of Quantum LDPC Codes. ISTC (2023)
Pau Salvador, Vicenç Almenar, Juan Luis Corral, Javier Valls, María José Canet
Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links. Sensors 23 (10) (2023)
Javier Valls, Francisco Garcia-Herrero, Nithin Raveendran, Bane Vasic
Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes. IEEE Access 9 (2021)
Julián S. Bruno, Vicenç Almenar, Javier Valls
FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems. Microprocess. Microsystems 64 (2019)
Javier Valls, Vicente Torres, María José Canet, Francisco Miguel Garcia-Herrero
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Garcia-Herrero
Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems. Circuits Syst. Signal Process. 38 (4) (2019)
J. M. Català-Pérez, Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls, David Declercq
Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes. Circuits Syst. Signal Process. 38 (11) (2019)
Vicente Torres, Javier Valls, María José Canet, Francisco Garcia-Herrero
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). NEWCAS (2018)
Roberto Llorente, Maria Morant, Julián S. Bruno, Vicenç Almenar, Juan Luis Corral, Jose M. Fuster, Javier Valls
Multidimensional Multiplexing in Multicore Fibre for Hybrid Optical Backhaul provision: The XCORE Approach. ICTON (2018)
Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Miguel Garcia-Herrero
High-Throughput One-Channel RS(255, 239) Decoder. DSD (2018)
Vicente Torres, Javier Valls, Richard Lyons
Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks]. IEEE Signal Process. Mag. 34 (6) (2017)
Vicente Torres, Javier Valls
A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. IEEE Trans. Very Large Scale Integr. Syst. 25 (9) (2017)
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
High-Performance NB-LDPC Decoder With Reduction of Message Exchange. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Julián S. Bruno, Vicenç Almenar, Javier Valls, Juan L. Corral
Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser. JOCN 7 (11) (2015)
Jesus Omar Lacruz, Francisco Garcia-Herrero, David Declercq, Javier Valls
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma José Canet, Javier Valls, Asuncion Perez-Pascual
A 630 Mbps non-binary LDPC decoder for FPGA. ISCAS (2015)
Francisco Garcia-Herrero, David Declercq, Javier Valls
Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes. IEEE Commun. Lett. 18 (5) (2014)
Francisco Garcia-Herrero, David Declercq, Javier Valls
A symbol flipping decoder for NB-LDPC relying on multiple votes. ISTC (2014)
J. M. Català-Pérez, Francisco Garcia-Herrero, Javier Valls, K. Liu, S. Lin
Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree. IEEE Commun. Lett. 18 (12) (2014)
Francisco Garcia-Herrero, Erbao Li, David Declercq, Javier Valls
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Fabian Angarita, Javier Valls, Vicenç Almenar, Vicente Torres-Carot
Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Guillermo A. Jaquenod, Javier Valls, Javier Siman
Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. Int. J. Reconfigurable Comput. 2014 (2014)
Francisco Garcia-Herrero, María José Canet, Javier Valls
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Erbao Li, Francisco Garcia-Herrero, David Declercq, Kiran K. Gunnam, Jesus Omar Lacruz, Javier Valls
Low latency T-EMS decoder for non-binary LDPC codes. ACSSC (2013)
Francisco Garcia-Herrero, María José Canet, Javier Valls
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes. Circuits Syst. Signal Process. 32 (2) (2013)
Francisco Garcia-Herrero, Ma José Canet, Javier Valls
High-speed NB-LDPC decoder for wireless applications. ISPACS (2013)
Vicente Torres-Carot, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls
Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. ICECS (2012)
María José Canet, Vicenc Almenar-Terre, Santiago J. Flores, Javier Valls
Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles. J. Signal Process. Syst. 68 (3) (2012)
Fabian Angarita, Vicente Torres-Carot, Asuncion Perez-Pascual, Javier Valls
High-throughput FPGA-based emulator for structured LDPC codes. ICECS (2012)
Fabian Angarita, Trinidad Sansaloni, Asuncion Perez-Pascual, Javier Valls
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. J. Signal Process. Syst. 68 (2) (2012)
Fabian Angarita, José Marín-Roig, Vicenç Almenar, Javier Valls
Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation. IET Commun. 6 (16) (2012)
María José Canet, Javier Valls, Vicenç Almenar, José Marín-Roig
FPGA implementation of an OFDM-based WLAN receiver. Microprocess. Microsystems 36 (3) (2012)
Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012)
Francisco Garcia-Herrero, María José Canet, Javier Valls, Mark F. Flanagan
Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes. IEEE Commun. Lett. 16 (6) (2012)
Francisco Garcia-Herrero, María José Canet, Javier Valls
Decoder for an enhanced serial generalized bit flipping algorithm. ICECS (2012)
Roberto Gutierrez, Vicente Torres-Carot, Javier Valls
Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method. IEEE Trans. Circuits Syst. II Express Briefs (8) (2012)
Fabian Angarita, Trinidad Sansaloni, María José Canet, Javier Valls
Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. J. Signal Process. Syst. 66 (2) (2012)
Francisco Garcia-Herrero, Javier Valls, Pramod Kumar Meher
High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits Syst. Signal Process. 30 (6) (2011)
Roberto Gutierrez, Javier Valls
Low Cost Hardware Implementation of Logarithm Approximation. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. J. Signal Process. Syst. 56 (1) (2009)
Roberto Gutierrez, Javier Valls, Asuncion Perez-Pascual
FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. FPL (2009)
Fabian Angarita, Ma José Canet, Trinidad Sansaloni, Vicenç Almenar, Javier Valls
Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN. J. Circuits Syst. Comput. 18 (7) (2009)
A. Perez-Pascual, T. Sansaloni, Vicente Torres-Carot, Vicenc Almenar-Terre, Javier Valls
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. J. Signal Process. Syst. 56 (1) (2009)
Pramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna
50 Years of CORDIC: Algorithms, Architectures, and Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Roberto Gutierrez, Javier Valls
) Using Look-Up Table Methods for Communication Applications. J. Signal Process. Syst. 56 (1) (2009)
José Marín-Roig, Vicenç Almenar, Javier Valls, Ma José Canet
64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm. ICECS (2008)
Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. J. Signal Process. Syst. 52 (1) (2008)
Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. J. Signal Process. Syst. 52 (2) (2008)
Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres-Carot, Vicenç Almenar, José F. Toledo, Javier Valls
FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. IEEE Trans. Educ. 50 (3) (2007)
María José Canet, Vicenç Almenar, José Marín-Roig, Javier Valls
Time Synchronization for the IEEE 802.11a/g WLAN Standard. PIMRC (2007)
Ma José Canet, Vicenç Almenar, Santiago J. Flores, Javier Valls
Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard. EUSIPCO (2007)
Roberto Gutierrez, Javier Valls
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. FPL (2007)
A. Perez-Pascual, T. Sansaloni, Vicente Torres, Vicenç Almenar, Javier Valls
Design of an efficient digital down-converter for a SDR-based DVB-S receiver. ECCTD (2007)
T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. J. VLSI Signal Process. 47 (2) (2007)
Javier Valls, Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres, Vicenç Almenar
The use of CORDIC in software defined radios: a tutorial. IEEE Commun. Mag. 44 (9) (2006)
Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
Design of high performance timing recovery loops for communication applications. SiPS (2006)
Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo
Statistical Power Estimation for FPGA. FPL (2005)
Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. FPL (2005)
Ma José Canet, Ian J. Wassell, Javier Valls, Vicenç Almenar
Performance evaluation of fine time synchronizers for WLANs. EUSIPCO (2005)
Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls
Power analysis and estimation tool integrated with XPOWER. FPGA (2004)
Ma José Canet, Felip Vicedo, Vicenç Almenar, Javier Valls, Eduardo R. de Lima
A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. PIMRC (2004)
Javier Valls, Eduardo I. Boemo
Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers. IEEE Trans. Circuits Syst. II Express Briefs 50 (6) (2003)
T. Sansaloni, Javier Valls, Keshab K. Parhi
Digit-Serial Complex-Number Multipliers on FPGAs. J. VLSI Signal Process. 33 (1-2) (2003)
Javier Valls, Martin Kuhlmann, Keshab K. Parhi
Evaluation of CORDIC Algorithms for FPGA Design. J. VLSI Signal Process. 32 (3) (2002)
A. Perez-Pascual, T. Sansaloni, Javier Valls
FPGA-based radix-4 butterflies for HIPERLAN/2. ISCAS (3) (2002)
A. Perez-Pascual, T. Sansaloni, Javier Valls
FPGA based on-line complex-number multipliers. ICECS (2001)
T. Sansaloni, A. Perez-Pascual, Javier Valls
Distributed arithmetic radix-2 butterflies for FPGA. ICECS (2001)
Trinidad Sansaloni, Javier Valls, Keshab K. Parhi
FPGA-based digit-serial complex number multiplier-accumulator. ISCAS (2000)
A. Perez-Pascual, Javier Valls, Marcos M. Peiró
Efficient complex-number multipliers mapped on FPGA. ICECS (1999)
Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo
Fast FPGA-based pipelined digit-serial/parallel multipliers. ISCAS (1) (1999)
Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. ICECS (1999)
Javier Valls, Marcos M. Peiró, Trinidad Sansaloni, Eduardo I. Boemo
Design and FPGA implementation of digit-serial FIR filters. ICECS (1998)